1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing dielectric layers on a substrate.
2. Background of the Invention
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526, entitled “Plasma-Enhanced CVD Process Using TEOS for Depositing Silicon Oxide”, which is incorporated by reference herein. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma of highly reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.25 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant<2.5) to reduce the capacitive coupling between adjacent metal lines. Liner/barrier layers have been used between the conductive materials and the insulators to prevent diffusion of byproducts such as moisture onto the conductive material as described in International Publication Number WO 99/41423, published on Aug. 17, 1999. For example, moisture that can be generated during formation of a low k insulator readily diffuses to the surface of the conductive metal and increases the resistivity of the conductive metal surface. A barrier/liner layer formed from organosilicon or organosilane nitride materials can block the diffusion of the byproducts. However, the barrier/liner layers typically have dielectric constants that are greater than about 2.5, and the high dielectric constants result in a combined insulator that may not significantly reduce the dielectric constant.
FIG. 1A-1E illustrates a three-layer deposition PECVD process for depositing a PECVD lining layer 2 of the oxidized organosilane or organosiloxane polymer as described in International Publication Number WO 99/41423. The lining layer 2 acts as an isolation layer between a subsequent layer 7 and the underlying substrate surface 6 and metal lines 8, 9, 10 formed on the substrate surface. The layer 7 is capped by a PECVD capping layer 12 of the oxidized organosilane or organosiloxane polymer. The PECVD process deposits a multi-component dielectric layer, wherein an carbon containing silicon dioxide (SiO2) is first deposited on the patterned metal layer having metal lines 8, 9, 10 formed on substrate 6.
Referring to FIG. 1A, the PECVD lining layer 2 is deposited by the plasma enhanced reaction of an organosilane or organosiloxane compound such as methylsilane, CH3SiH3, and an oxidizing gas such as N2O in the presence of an inert gas, such as argon, at a temperature of approximately −20° C to 40° C. The oxidized organosilane or organosiloxane layer is then cured. The deposited PECVD lining layer 2 (at about 2000 Å per minute) has improved barrier characteristics for the subsequent deposition of the layer 7 shown in FIG. 1B. The lining layer obtained from methylsilane has sufficient C—H bonds to be hydrophobic, and is an excellent moisture barrier. A low K dielectric layer 7 is then deposited on the liner layer 2 by the reaction of a silane compound and hydrogen peroxide (H2O2) at a temperature below 200° C. at a pressure of about 0.2 to about 5 Torr during deposition of the layer 7. The layer 7 may be partially cured as shown in FIG. 1C to remove solvents such as water prior to deposition of a cap layer 12 as shown in FIG. 1D. Curing is performed by pumping down a reaction under an inert gas atmosphere under 10 Torr.
Conventional liner layers, such as silicon nitride (SiN), have higher dielectric constants than silicon oxides, and the combination of low k dielectric layers with high k dielectric liner layers provides little or no improvement in the overall stack dielectric constant and capacitive coupling. Referring to FIG. 1D, after deposition of the layer 7, an optional capping layer 12 may be deposited on the low k dielectric layer 7 by the plasma enhanced reaction of an organosilane or organosiloxane compound and an oxidizing gas such as N2O. Referring to FIG. 1E, after deposition of the capping layer, if any, the deposited layers are cured in a furnace or another chamber to drive off remaining solvent or water. The capping layer 12 is also an oxidized organosilane or organosiloxane film that has good barrier properties and has a dielectric property of about 3.0. Both the liner layer 2 and the cap layer 12 have a dielectric constant greater than 3.0 and the high dielectric constant layers substantially detract from the benefit of the low k dielectric layer 7.
As devices get smaller, liner layers and cap layers having relatively high dielectric constants contribute more to the overall dielectric constant of a multi-component dielectric layer. Additionally, the smaller device geometries result in an increase in parasitic capacitance between devices. Parasitic capacitance between metal interconnects on the same or adjacent layers in the circuit can result in crosstalk between the metal lines or interconnects and/or resistance-capacitance (RC) delay, thereby reducing the response time of the device and degrading the overall performance of the device. The effects of parasitic capacitance between metal interconnects on the same or adjacent layers in the circuit is especially of concern as the current state of the art circuits can employ 4 to 5 levels of interconnection, while next generation devices may require 6, 7, or possibly 8 levels of interconnection.
Lowering the parasitic capacitance between metal interconnects separated by dielectric material can be accomplished by either increasing the thickness of the dielectric material or by lowering the dielectric constant of the dielectric material. Increasing the thickness of the dielectric materials, however, does not address parasitic capacitance within the same metallized layer or plane. As a result, to reduce the parasitic capacitance between metal interconnects on the same or adjacent layers, one must change the material used between the metal lines or interconnects to a material having a lower dielectric constant than that of the materials currently used, i.e., k≈3.0.
Therefore, there remains a need for dielectric layers having dielectric constants below about 2.5 with good adhesion properties.